1. Technical Field
Various embodiments of the invention relate to a semiconductor integrated circuit and, more particularly, to a delay locked loop (DLL) circuit of a semiconductor memory apparatus.
2. Related Art
In general, a synchronous semiconductor memory apparatus operates by receiving a clock inputted from outside. When an internal circuit of the semiconductor memory apparatus operates by receiving the clock, delay occurs in the clock. For example, delay may occur in an input clock buffer, a line loading, a data output buffer, and other circuits and lines through which the clock passes, such as logic circuits. Such delay may cause phase difference between the clock inputted externally and a clock used internally.
A DLL circuit corrects the internal delay amount of the semiconductor memory apparatus so that the clock inputted from outside of the semiconductor memory apparatus and a signal outputted from the semiconductor memory apparatus have the same phase.
Such a DLL circuit is a clock generation device for compensating a skew between an external clock and data or between an external clock and an internal clock, and is used in a synchronous semiconductor memory apparatus.